Available for postdoctoral & research collaborations
Hazoor Ahmad, PhD
Senior Research Officer at NASTP Alpha, working on FPGA-based Radar Signal Processing and Data Processing for Search Radar. Ph.D. research in hardware acceleration for deep learning at the edge; ongoing work in Neural Architecture Search for radar and power-systems applications.
About
Electrical engineer with a Ph.D. focused on hardware acceleration for deep learning at the edge — FPGA/RISC-V accelerator design, model compression, and cryptographic hardware. I joined NASTP Alpha as a Systems Engineer in March 2024 and was promoted to Senior Research Officer in August 2025, delivering FPGA-based Radar Signal Processing (MATLAB, PS, and PL implementations on the Xilinx ZCU102) and a Data Processor for Search Radar systems, including two rounds of On-the-Job Training with our partner company VirtuaLabs Srl in Rome, Italy.
Alongside this role, I run independent research on Neural Architecture Search for compact, efficient deep-learning models — applied to Power Quality classification and to Direction-of-Arrival estimation for digital array radars. Earlier work includes RISC-V cryptography extensions (AES, SM4, SHA-2, SM3, Galois Field arithmetic) and FPGA-based computer vision on Ultra96 and STM32 platforms.
Current role
NASTP Alpha — Rawalpindi, Pakistan
8 AUG 2025 – PRESENT
Senior Research Officer
- Hardware (HDL) implementation of Radar Signal Processing (RSP) for Search Radar; now implementing RSP on the PL (programmable-logic) side of the FPGA.
- Data Processor for Search Radar — tracking, track management, track filtering, plot extraction, and detection management.
- Selected for On-the-Job Training (OJT1 & OJT2) with partner company VirtuaLabs Srl, Rome, Italy — Nov–Dec 2025 and Apr 2026, ~5–6 weeks on-site in total.
Previously — Systems Engineer
10 MAR 2024 – 7 AUG 2025
- Completed international training in Radar, Space & EW Technologies (VirtuaLabs, Italy) — certified 26 Sep 2024.
- Initial assignment: Payload Controller Module development, Space Division.
- Radar Signal Processing (RSP) for Search Radar — MATLAB- and PS-based implementation on the Xilinx ZCU102.
Research highlights
Hardware acceleration for deep learning at the edge
Ph.D. thesis work: design-space exploration and model compression for deep-learning accelerators (SuperSlash), RISC-V-based cryptography extensions, and FPGA/microcontroller deployments for image classification and object detection.
NAS for Power Quality classification
Bayesian-optimization-driven Neural Architecture Search over a newly built, Butterworth-filtered PQ dataset (8-channel concatenation). Twelve input/architecture configurations were swept, each via 5-fold cross-validation, before fine-tuning the strongest candidates.
NAS for DoA estimation — digital array radars
NAS-DoA (end-to-end) and NAS-SubSpaceNet (subspace-feature-augmented, CNN- and encoder-decoder-based) architectures, searched against a joint accuracy/size objective F = α·RMSE + β·Model Size for real-time, embedded-radar deployment.
Selected publications
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Investigation of Vibration’s Effect on Driver in Optimal Motion Cueing Algorithm
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SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume
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Systimator: A Design Space Exploration Methodology for Systolic Array-based CNNs Acceleration on the FPGA-based Edge Nodes
Education
Skills & credentials
Languages & tools
Python
MATLAB
C / C++
Vivado
Quartus / ISE
Certifications
- RADAR, Space & EW Technical Training — VirtuaLabs, Italy (2024)
- Artificial Intelligence — NIAIS, Pakistan (2021–22)
- Python — NIAIS, Pakistan (2021–22)
Memberships & service
- IEEE Student Member
- PEC (Pakistan Engineering Council)
- Industrial Advisory Board — School of Electrical Engineering, Minhaj University Lahore